I finally got ahold front loader NES with this problem. It's a silly bug in the FPGA firmware. When I enabled the PLL I mistakenly connected the FPGA PLL reset to the console reset signal. So when the console reset time is extended by changing the capacitor on the motherboard, the reset time of the FPGA is extended too.
Fortunately there is a simple fix. There is a redundant reset signal generated on the NESRGB board already. This is because the Famicom consoles don't reset the PPU, the reset pin is tied to the 5V supply on these consoles. The fix is to just cut off the RESET pin off the NESRGB board assembly, isolate it, and connect it to +5V.
Here's the procedure:
1. Cut pin 22 (RESET#) off the NESRGB board assembly.

2. Put some electrical tape over pin 22 of the socket on the motherboard.

3. Solder a 1k resistor between pin 40 (+5V) and pin 22 (RESET#) on the NESRGB board. If you don't have a resistor handy, just make a direct connection with some wire. Install the NESRGB board back in place on the motherboard and use a multimeter to measure the continuity between pin 22 on the motherboard and NESRGB board to make sure it's not connected.
