GBS 8200/8220 CFW Project

[AndehX]

Rama, I've noticed that ADC gain is not saved to a custom preset. If I adjust the ADC gain and save the preset, it then resets after I load the preset again.

[NoAffinity]

Rama, I've noticed that ADC gain is not saved to a custom preset. If I adjust the ADC gain and save the preset, it then resets after I load the preset again.

I have noticed this too.

Also, rama, could you provide a brief explanation of how to save/load more than one custom preset? It seems that the GBS boots to whatever the last settings were, and clicking the "Save Custom Preset", or any of the Custom Preset Slots 1-5 is no longer doing anything. (sorry if these aren't exactly how they're labeled, I'm at work and don't have a GBS in front of me.)

[rama]

rama - can you please clarify this. I don't quite understand.

By the way, I just noticed that on some GBS board designs, C41 is more crowded. It can be replaced by C43.

There is no space around C41 on some boards, so soldering a parallel cap would be difficult. Use the location C43 instead

Rama, I've noticed that ADC gain is not saved to a custom preset. If I adjust the ADC gain and save the preset, it then resets after I load the preset again.

Just tested and this still works as it should.
So I suppose you guys haven't selected the custom preset slot, maybe?
The procedure is:
Do your customizations, select one of the "Custom Presets" slots, hit "Save Custom Preset".

When you "Load Custom Preset" now, or when you reboot the device, it will work. ADC gain included :p

If that fixes your issue, maybe I should auto select a custom preset slot when the user hits save?

[AndehX]

Just tested and this still works as it should.
So I suppose you guys haven't selected the custom preset slot, maybe?
The procedure is:
Do your customizations, select one of the "Custom Presets" slots, hit "Save Custom Preset".

When you "Load Custom Preset" now, or when you reboot the device, it will work. ADC gain included :p

If that fixes your issue, maybe I should auto select a custom preset slot when the user hits save?

Well I have Custom preset 1 set to load automatically on start up. But when I make changes to the ADC gain, and click "Save custom preset" the ADC will reset back to default after clicking "Load custom preset"

[NoAffinity]

rama - can you please clarify this. I don't quite understand.

By the way, I just noticed that on some GBS board designs, C41 is more crowded. It can be replaced by C43.

There is no space around C41 on some boards, so soldering a parallel cap would be difficult. Use the location C43 instead

Rama, I've noticed that ADC gain is not saved to a custom preset. If I adjust the ADC gain and save the preset, it then resets after I load the preset again.

Just tested and this still works as it should.
So I suppose you guys haven't selected the custom preset slot, maybe?
The procedure is:
Do your customizations, select one of the "Custom Presets" slots, hit "Save Custom Preset".

When you "Load Custom Preset" now, or when you reboot the device, it will work. ADC gain included :p

If that fixes your issue, maybe I should auto select a custom preset slot when the user hits save?

Okay, understood on C41/C43.

WRT to custom presets, that's extremely helpful. When you "Load Custom Preset", do you click that first then click the custom preset you want to load? If that's how it works, that then makes perfect sense now that I know. You have to press either the save or load button first then choose which preset you want to save or load.

I had been clicking "Save Custom Preset", then looking at the readout for some indication of which custom preset it was saving it to, lol. But, maybe if it can be automated to save to the next available slot that doesn't already have a preset saved to it, and report which one it was saved to, that would be more intuitive. Then you would simply click the button for preset 1-5 to load it. But, maybe it's a lot more work for not a lot of benefit, and like I said, once you know how it currently works, it makes great sense.

[rama]

Well I have Custom preset 1 set to load automatically on start up. But when I make changes to the ADC gain, and click "Save custom preset" the ADC will reset back to default after clicking "Load custom preset"

It works here, doing it exactly as you described. So idk ><

NoAffinity:
It doesn't require so many steps. The software simply needs to know which slot you want, so you select one slot first, or let it use the default slot 1.
You hit save and it saves to your slot. You hit load, and it loads from the slot.
That's all really :p

Both of you:
Please ensure that the SPIFFS filesystem is working. If it says anything about not being able to load or save, SPIFFS isn't enabled in the IDE!

[AndehX]

Ok that's weird, now it seems to be working. After loading my custom preset, clicking "Auto gain adjust toggle" doesn't seem to do anything anymore. Not sure why it's just decided to work lol. Maybe the scaler needed restarting before the ADC adjustment took affect? I dunno...

[rama]

Auto gain is a little tricky to manage, especially across preset changes.
The thing with it is that it needs to start at a very high gain level, then work downwards from that.
I think I decided to make it stop adjusting for custom presets, because the preset is supposed to be adjusted already.
If you toggle it off>on once more, it'll restart though.

The other thing with auto gain is that it doesn't currently support Component sources.
The debug bus readouts are different for YPbPr, but I'm sure it can be done there as well.

[AndehX]

so do you recommend manually adjusting the brightness for custom presets, instead of using auto?

[NoAffinity]

So, life got in the way last night, so I've just gotten around to testing limited range vs. full range at various points, and honestly, I didn't have to tweak anything, it just works. So, not sure what I did wrong, but there some interesting results along the process chain which I thought worth sharing. I hooked things up, did a quick auto-gain, centered the image, and then saved it to slot 1 now that I understand better how to actually do that.

SNES SCART/RGBS input at GBS-8200 CFW, how it appears on the TV:


How it appears on OBS, with Magewell reporting full range input and limited range output, with no intervention on my part. It senses the input and apparently also what OBS is set to receive (OBS set to 709 and partial).


How playback appears, in both VLC and WMP.


How playback appears in Quicktime.


How playback appears once uploaded to YT.
https://youtu.be/iKAXBavA84A

[AndehX]

If you have an nvidia graphics card, right click desktop, go to nvidia settings, and then at the bottom, go to Adjust video color settings. Make sure it's set to "With the nvidia settings" and set it to Full. That should fix your WMP and VLC issue.

[AndehX]

Quick observation: I've noticed that scanlines in the 1280x720 preset appear thicker at the top of the image, and thinner at the bottom.

[rama]

Well, that looks like it's fixed, whatever it was

Is Dreamcast working now btw?

AndehX:
If you have the 240p test suite and a good eye, then manual adjustment is better.
Auto gets the gain right for the ADC, but it doesn't know about the rest of the chain.
Also it's a bit beta still. I've seen it go too far occasionally.
Then the algorithm crosses a boundary and it keeps getting worse and worse (way too dark).
I still need to work on it :p

The scanlines are even for the scaling and line count in all presets.
If they appear uneven, maybe something else is scaling? Or maybe the image content makes it appear uneven.
Scanlines look horrible here in 720p anyway though, but idk if it's my display.

[AndehX]

The 720p scanline thing isn't really a big issue anyway, because scanlines will always appear uneven until there's a 1080p preset or some kind of 1080p integer preset like 540p or something

[NoAffinity]

@AndehX - It's a AMD video card, but I went through AMD's calibration process and it is now improved. Thank you for that suggestion.

@rama - I just tried removing the 100ohm sync->ground (from RGBS inputs) resistors, and DC is still flakey. With resistors, I get no signal. Without resistors it is constantly losing sync.

[Higgy]

I just been looking over my Dreamcast SCART cable. RGB has caps. Sync is wired to CompositeSync.
There was a wire for Composite Video so I re-wired Sync to Composite Video but got no picture.

I changed back to Composite Sync in my Dreamcast SCART and have added back in my Sync Stripper (also to help with Megadrive) and I get a rock solid picture.

AndehX - you get perfect picture on Dreamcast. Remind us, are you running a Sync Splitter? Have you added 1nF caps? Thanks

rama -some posts back regarding the UI, dont worry your ICONS are big enough, it is my mobile phone's browser. If I 'tap' too quickly it zooms in on the webpage and then the button under my finger was the [+] instead of the [-] The 4x pixel shift adjustment shall mean I am not not 'tapping' too much

[NoAffinity]

To be clear, I'm testing DC VGA ouptut into GBS-8200. That's what I was referring to above. With sync->ground resistors completely removed from the RGBS inputs, I get flakey DC on the VGA input. With resistor in place on the RGBS inputs, I get no DC VGA signal.

I assumed you guys are using SCART cables, well AndehX at least, since his video showed DC @ 480i.

[AndehX]

AndehX - you get perfect picture on Dreamcast. Remind us, are you running a Sync Splitter? Have you added 1nF caps? Thanks

I'm not using the sync stripper anymore since I added the 1nf caps.

[Higgy]

I just tried my other GBS V4.1 no sync stripper 1nF caps - Dreamcast sync is still bad?

The only thing I re-used was the actual ESP8266 controller as I am still waiting for a PLCC socket to build another complete unit.
Unit and both GBS's seem ok on other consoles but I could look at another PSU? currently using a mobile phone 5V charger with USB-barrel connector.

[rama]

There might be a problem with the DC in VGA mode then. I can't test it here, no console.
I expect the console outputs real VGA with separate HSync and VSync.
This is very easy to lock on to, software wise.

Maybe I could see an info mode log of it with shaky sync?

[maxtherabbit]

the dreamcast does not output composite video OR composite sync when in 31kHz mode - only separate H and V syncs

[NoAffinity]

Maybe I could see an info mode log of it with shaky sync?

In the serial monitor I get this:

Spoiler

> 1349: 5:0
> 1349: 6:0
> 1349: 7:0
> 1349: 0:0
> 1349: 1:0
> 1349: 2:0
> 1349: 3:0
> 1349: 4:1
> 1349: 5:1
> 1349: 6:1
> 1349: 7:1
> 1349: 0:1
> 1349: 1:1
> 1349: 2:1
> 1349: 3:1
> 1856: 4:0
> 1856: 5:0
> 1856: 6:0
> 1856: 7:0
> 1856: 0:0
> 1856: 1:0
> 1856: 2:0
> 1856: 3:0
> 1349: 4:1
> 1349: 5:1
> 1349: 6:1
> 1349: 7:1
> 1349: 0:1
> 1349: 1:1
> 1349: 2:1
> 1349: 3:1
> 1349: 4:0
> 1349: 5:0
> 1349: 6:0
> 1349: 7:0
> 1349: 0:0
> 1349: 1:0
> 1349: 2:0
> 1349: 3:0
> 1856: 4:1
> 1856: 5:1
> 1856: 6:1
> 1856: 7:1
> 1856: 0:1
> 1856: 1:1
> 1856: 2:1
> 1856: 3:1
> 1349: 4:0
> 1349: 5:0
> 1349: 6:0
> 1349: 7:0
> 1349: 0:0
> 1349: 1:0
> 1349: 2:0
> 1349: 3:0
> 1349: 4:1
> 1349: 5:1
> 1349: 6:1
> 1349: 7:1
> 1349: 0:1
> 1349: 1:1
> 1349: 2:1
> 1349: 3:1
> 1856: 4:0
> 1856: 5:0
> 1856: 6:0
> 1856: 7:0
> 1856: 0:0
> 1856: 1:0
> 1856: 2:0
> 1856: 3:0
> 1349: 4:1
> 1349: 5:1
> 1349: 6:1
> 1349: 7:1
> 1349: 0:1
> 1349: 1:1
> 1349: 2:1
> 1349: 3:1
> 1349: 4:0
> 1349: 5:0
> 1349: 6:0
> 1349: 7:0
> 1349: 0:0
> 1349: 1:0
> 1349: 2:0
> 1349: 3:0
> 1856: 4:1
> 1856: 5:1
> 1856: 6:1
> 1856: 7:1
> 1856: 0:1
> 1856: 1:1
> 1856: 2:1
> 1856: 3:1
> 1349: 4:0
> 1349: 5:0
> 1349: 6:0
> 1349: 7:0
> 1349: 0:0
> 1349: 1:0
> 1349: 2:0
> 1349: 3:0
> 1349: 4:1
> 1349: 5:1
> 1349: 6:1
> 1349: 7:1
> 1349: 0:1
> 1349: 1:1
> 1349: 2:1
> 1349: 3:1
> 1856: 4:0
> 1856: 5:0
> 1856: 6:0

and from Print Infos, I get this:

Spoiler

> 1349: 3:1
> 1349: 4:0
> 1349: 5:0
> 1349: 6:0
> 1349: 7:0
> 1349: 0:0
> 1349: 1:0
> 1349: 2:0
> 1349: 3:0
> 1856: 4:1
> 1856: 5:1
> 1856: 6:1
> 1856: 7:1
> 1856: 0:1
> 1856: 1:1
> 1856: 2:1
> 1856: 3:1
> 1349: 4:0
> 1349: 5:0
> 1349: 6:0
> 1349: 7:0
> 1349: 0:0
> 1349: 1:0
> 1349: 2:0
> 1349: 3:0
> 1349: 4:1
> 1349: 5:1
> 1349: 6:1
> 1349: 7:1
> 1349: 0:1
> 1349: 1:1
> 1349: 2:1
> 1349: 3:1
h: 0 v: 0 PLL.00 A:878686 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:32752 L:3
> 1856: 4:0
h: 0 v: 0 PLL.00 A:878686 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:33648 L:276
h: 0 v: 0 PLL.00 A:878686 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 148 s:ff W:31 F:33648 L:9
> 1856: 5:0
h: 0 v: 0 PLL.00 A:878686 S:02.18 I:00 D:0627 m:15 ht:1855 vt:525 hpw: 147 s:ff W:31 F:32976 L:265
h: 0 v: 0 PLL.01 A:878686 S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:31632 L:9
> 1856: 6:0
h: 0 v: 0 PLL.01 A:878686 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:33648 L:290
h: 0 v: 0 PLL.02 A:878686 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:32304 L:4
h: 0 v: 0 PLL.03 A:878686 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:30960 L:9
h: 0 v: 0 PLL.03 A:878686 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 148 s:ff W:31 F:29616 L:4
h: 0 v: 0 PLL.03 A:878686 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 145 s:ff W:31 F:28272 L:8
> 1856: 7:0
h: 0 v: 0 PLL.04 A:878686 S:02.18 I:00 D:0627 m:15 ht:1857 vt:525 hpw: 148 s:ff W:31 F:33648 L:264
h: 0 v: 0 PLL.04 A:878686 S:02.18 I:00 D:0637 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:32304 L:3
h: 0 v: 0 PLL.04 A:878686 S:02.18 I:00 D:0637 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:30960 L:8
> 1856: 0:0
h: 0 v: 0 PLL.04 A:878686 S:02.18 I:00 D:0666 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:33648 L:263
h: 0 v: 0 PLL.04 A:878686 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:32304 L:8
> 1856: 1:0
h: 0 v: 0 PLL.04 A:878687 S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 148 s:ff W:31 F:32976 L:266
h: 0 v: 0 PLL.04 A:878687 S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:31632 L:4
> 1856: 2:0
h: 0 v: 0 PLL.04 A:878687 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 148 s:ff W:31 F:33648 L:308
h: 0 v: 0 PLL.04 A:878687 S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:32304 L:3
h: 0 v: 0 PLL.03 A:878687 S:02.18 I:00 D:06a7 m:15 ht:1855 vt:525 hpw: 147 s:ff W:31 F:30960 L:8
> 1856: 3:0
h: 0 v: 0 PLL.03 A:878688 S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:33648 L:372
h: 0 v: 0 PLL.03 A:878688 S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:32304 L:4
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 149 s:ff W:31 F:30960 L:9
> 1349: 4:1
h: 0 v: 0 PLL.02 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1350 vt:525 hpw: 105 s:ff W:31 F:32976 L:289
h: 0 v: 0 PLL.02 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:31632 L:3
> 1349: 5:1
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:33648 L:298
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:32304 L:8
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:30960 L:9
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:29616 L:8
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:28272 L:9
> 1349: 6:1
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1600 vt:525 hpw: 103 s:ff W:31 F:33648 L:261
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1601 vt:525 hpw: 100 s:ff W:31 F:32304 L:4
> 1349: 7:1
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1929 vt:405 hpw: 159 s:ff W:31 F:33648 L:261
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1932 vt:319 hpw: 158 s:ff W:31 F:32304 L:9
> 1349: 0:1
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32976 L:381
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:33648 L:10
> 1349: 1:1
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33648 L:262
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 106 s:ff W:31 F:32304 L:4
> 1349: 2:1
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:33648 L:263
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1350 vt:525 hpw: 106 s:ff W:31 F:32304 L:4
> 1349: 3:1
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33648 L:262
h: 0 v: 0 PLL.02 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:32304 L:9
> 1349: 4:0
h: 0 v: 0 PLL.01 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 106 s:ff W:31 F:32976 L:284
h: 0 v: 0 PLL.01 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:31632 L:9
> 1349: 5:0
h: 0 v: 0 PLL.02 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:33648 L:394
h: 0 v: 0 PLL.01 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32304 L:9
h: 0 v: 0 PLL.02 A:878689 S:02.18 I:00 D:0627 m:15 ht:1350 vt:525 hpw: 105 s:ff W:31 F:30960 L:9
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:29616 L:8
> 1349: 6:0
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0666 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:33648 L:270
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:32304 L:3
> 1349: 7:0
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0637 m:15 ht:1066 vt:525 hpw: 12 s:ff W:31 F:33648 L:261
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1065 vt:525 hpw: 12 s:ff W:31 F:32304 L:8
> 1349: 0:0
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32976 L:264
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1348 vt:525 hpw: 108 s:ff W:31 F:31632 L:8
> 1349: 1:0
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33648 L:263
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32304 L:3
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:30960 L:8
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:29616 L:4
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:28272 L:8
> 1349: 2:0
h: 0 v: 0 PLL.04 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33648 L:262
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32304 L:8
> 1349: 3:0
h: 0 v: 0 PLL.03 A:878689 S:02.18 I:00 D:06e6 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32976 L:263
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:06e6 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:33648 L:10
> 1856: 4:1
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1857 vt:525 hpw: 146 s:ff W:31 F:33648 L:274
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:32304 L:9
> 1856: 5:1
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:33648 L:287
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 146 s:ff W:31 F:32304 L:4
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1858 vt:525 hpw: 147 s:ff W:31 F:30960 L:8
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:29616 L:4
h: 0 v: 0 PLL.03 A:87868a S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 146 s:ff W:31 F:28272 L:8
> 1856: 6:1
h: 0 v: 0 PLL.03 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:33648 L:263
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:32304 L:4
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:30960 L:8
> 1856: 7:1
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:2231 vt:525 hpw: 10 s:ff W:31 F:32976 L:346
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1468 vt:525 hpw: 10 s:ff W:31 F:32304 L:4
> 1856: 0:1
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 144 s:ff W:31 F:33648 L:263
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1855 vt:525 hpw: 147 s:ff W:31 F:32304 L:8
> 1856: 1:1
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 146 s:ff W:31 F:32752 L:1528
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 147 s:ff W:31 F:33536 L:11
> 1856: 2:1
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1855 vt:525 hpw: 147 s:ff W:31 F:33552 L:261
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1856 vt:525 hpw: 145 s:ff W:31 F:33648 L:5
> 1856: 3:1
h: 0 v: 0 PLL.03 A:87868a S:02.18 I:00 D:0627 m:15 ht:1856 vt:525 hpw: 145 s:ff W:31 F:33648 L:261
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1857 vt:525 hpw: 147 s:ff W:31 F:33648 L:4
> 1349: 4:0
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33648 L:274
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32304 L:4
> 1349: 5:0
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:32976 L:442
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33648 L:9
> 1349: 6:0
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33648 L:262
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32304 L:3
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0666 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:30960 L:8
> 1349: 7:0
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1574 vt:525 hpw: 138 s:ff W:31 F:33800 L:263
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1576 vt:525 hpw: 12 s:ff W:31 F:33800 L:9
> 1349: 0:0
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33800 L:264
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 106 s:ff W:31 F:32456 L:3
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33800 L:10
> 1349: 1:0
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33128 L:264
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:31784 L:9
> 1349: 2:0
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1348 vt:525 hpw: 107 s:ff W:31 F:33800 L:259
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33800 L:4
> 1349: 3:0
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:33800 L:264
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:06e6 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:32456 L:3
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:31112 L:9
> 1349: 4:1
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33800 L:291
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:32456 L:4
> 1349: 5:1
h: 0 v: 0 PLL.01 A:87868a S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 107 s:ff W:31 F:33128 L:295
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:1349 vt:525 hpw: 105 s:ff W:31 F:33800 L:5
> 1349: 6:1
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1609 vt:525 hpw: 101 s:ff W:31 F:33800 L:263
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06b7 m:15 ht:1098 vt:525 hpw: 66 s:ff W:31 F:32456 L:4
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06a7 m:15 ht:1601 vt:525 hpw: 103 s:ff W:31 F:33800 L:10
> 1349: 7:1
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:2697 vt:373 hpw: 158 s:ff W:31 F:33800 L:264
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:06e6 m:15 ht:2700 vt:373 hpw: 155 s:ff W:31 F:32456 L:4
h: 0 v: 0 PLL.02 A:87868a S:02.18 I:00 D:0627 m:15 ht:2698 vt:312 hpw: 159 s:ff W:31 F:31112 L:8
> 1349: 0:1

Side note, I got the 10uf caps in, and put them on C23, C43, etc. It is a noticeable improvement to noise reduction!

[rama]

Okay, good news actually. It's just syncwatcher failing to dial in a fitting sampling clock.

640 480 60 Hz 31.475 kHz ModeLine "640x480" 25.18 640 656 752 800 480 490 492 525 -HSync -VSync

Last number is the actual number of vlines, so that is correct, VSync is working.
HSync may be unstable, or it's my routine failing to settle on a pixel clock.

I think I can simulate the video mode with my test PC, but it'll take a while :p

In the mean time, if you disable syncwatcher when it appear to be kind of stable + reading 512 vlines, maybe a picture will come up on screen.
It'll be unstable though :p

[NoAffinity]

It's working perfectly with syncwatcher disabled!

https://youtu.be/NsMskwlWTdA

Just to confirm, profiles should not be working with VGA input and it will default to pass thru even if you choose a profile?

Lastly, do you think it's possible to leave the 100ohm resistors in place, and it will still work with sync watcher disabled?

[PerplexedApe]

Can't seem to get this project working.

I think its wired up correctly. There is no signal to the monitor at all and the AP disappears and reappears in the wifi list on my phone. The video works if i remove the jumper. The serial monitor only gives me this.

14:32:34.236 -> starting
14:32:34.236 -> (WiFi) AP mode; Connect to 'gbscontrol', password 'qqqqqqqq'
14:32:34.270 -> userprefs open ok
14:32:34.270 -> presetPreference = 0
14:32:34.270 -> FrameTime Lock = 0
14:32:34.270 -> presetGroup = 0
14:32:34.305 -> frameTimeLockMethod = 0
14:32:34.305 -> enableAutoGain = 0
14:32:34.305 -> wantScanlines = 0
14:32:34.305 -> wantOutputComponent = 0
14:32:34.305 -> i2c: 0
14:32:34.612 -> <reset>
14:32:35.157 -> found: 82 getVideoMode: 1 input: 3
14:32:35.157 -> lost..
and just repeats. Any ideas on what I need to do?

[rama]

Yep, I use bypass mode for anything that's not 240p/480i or 480p (and the PAL equivalents).
Choosing presets and such has no effect, and much of the functionality on the web ui doesn't do anything.

This is because those modes are typically high res and in a good format for display.
It's perfectly fine to pass them on to the display like that, as you can see with the DC.

Implementing the full scaling pipeline is often difficult, and if you consider that there must be like 200 formats to support..
I think you can see why I make that choice

The termination resistor should be optional, in case something VGA should be connected.
That's why I always suggest using a through hole part and wind it around the S and G posts.
Also possible is a manual switch.
The final termination value is a part of the specification and should be followed.
If it works without it, okay, but keep in mind that 75 Ohm termination draws more current than the VGA source is designed for!

For the DC stability, I'll just fix the pixel clock algorithm. It wasn't too important before, but I guess I should support the Dreamcast better.
Currently, it's more fit to support much larger input resolutions (like 1280x1024, displaying perfectly fine here, as if no GBS was in the chain ).

[NoAffinity]

Sorry I'm a bit confused. You said you bypass anything that's not 240p/480i/480p? But DC via VGA is 480p isnt it?

Sent from my SM-G955U using Tapatalk

[rama]

Specifically, I bypass anything also that's pure VGA (H+V Sync). True that it can be 480p and I could scale it, but there's no need to.
Bypass mode looks great already and I don't think messing around with the image is a benefit :p

So yeah, full processing only for PAL, NTSC and their true progressive modes (EDTV).
Anything above EDTV (ie 720p) is bypassed and looks great, imo.

[NoAffinity]

Okay, I understand. I was fantasizing about doing some VGA scaling to the profile resolution options, and comparing to the OSSC and VP30. So, then is there really any benefit to be had by including the GBS in the chain for VGA sources?

I thought "okay well maybe just convenience, to have a VGA input connected and either an RGB or component input, connected, but as we've found when having both RGB and component connected simultaneously, there is a negative effect on the image quality.

And I'm not saying I disagree with your choice, just making sure I understand what the functionality is, with respect to VGA. As it sits currently, GBS-Control turns these devices into (if I may summarize):

Excellent, cost-effective scaler for 240p/480i/480p via Component and RGBS
Excellent fast deinterlacer
Low-lag scaler
Great intermediary device, for interfacing with other scalers (such as DVDO products) that don't have SCART inputs and/or don't accept RGBS natively
For GBS-8220, added functionality of powered pass-thru VGA splitter

With regard to the deinterlacing, it's certainly unique, and in a sense I think rivals other low-lag products. It looks astounding for 3D content. And for 2D content (which in and of itself is a bit of a unique bird in the 480i arena), the mild combing around 2D elements while the remainder of the image doesn't provide any noticeable signs of being deinterlaced, well that's just a cool way of processing it, imho.

Let me know if I missed any crucial features. In a sense, I'm doing this "labeling" of the purpose, so I don't keep looking at things that might represent scope creep for your vision.

[NoAffinity]

And, to backup the belief that GBS w/ GBS-Control CFW is indeed a low-lag solution and fast deinterlacer, I thought I'd do some lag testing. I think I've sampled enough comparisons here to definitely say that the processing time of the GBS w/ GBS-Control CFW is on par with the OSSC.

GBS CFW Lag Testing

Testing component input @ GBS, VGA vs. CRT
Process chain: SNES SCART output ->SB-2840->C2G 6x2 Component Matrix->Simultaneous component output to
->GBS-8200->Sync Master 930b VGA monitor
->Sony Trintron KV-27FV16 (240p/480i support only)

GBS CFW @ 1280x1024 (supported resolution for SM930b)

240p test suite @ 240p, 1 frame of delay on the GBS side:

Spoiler

240p test suite @ 480i, 2 frames of delay on the GBS side:

Spoiler

Testing component input @ GBS, LCD vs. CRT
Process chain: SNES SCART output ->SB-2840->C2G 6x2 Component Matrix->Simultaneous component output to
->GBS-8200-> OSSC Pass thru->HDMI output through various HDMI switches/splitters->TCL 49s405 LCD @ Game Mode
-> Sony Trintron KV-27FV16 (240p/480i support only)

GBS CFW @ 1280x1024

240p test suite @ 240p, 3 (2.5?) frames of delay on the GBS side:

Spoiler

240p test suite @ 480i, 3 (2.5?) frames of delay on the GBS side:

Spoiler

Testing component input @ GBS, VGA vs. CRT vs. LCD
Process chain: SNES SCART output ->SB-2840->C2G 6x2 Component Matrix->Simultaneous component output to
-> Sony Trintron KV-27FV16 (240p/480i support only)
->Powered VGA splitter (1 in, 2 out)
->GBS-8200-> OSSC Pass thru->HDMI output through various HDMI switches/splitters->TCL 49s405 LCD @ Game Mode
->Sync Master 930b VGA monitor

GBS CFW @ 1280x1024 (supported resolution for SM930b)

240p test suite @ 240p, 1 frame of delay on the GBS side:

Spoiler

240p test suite @ 480i, 2 frames of delay on the GBS side:

Spoiler

Testing SCART-direct input @ GBS, VGA vs. LCD
Process chain: SNES SCART output ->GBS-8200->Powered VGA splitter (1 in, 2 out)->Simultaneous ouput to
->OSSC Pass thru->HDMI output through various HDMI switches/splitters->TCL 49s405 LCD @ Game Mode
->Sync Master 930b VGA monitor

GBS CFW @ 1280x1024 (supported resolution for SM930b)

240p test suite @ 240p, no verifiable difference:

Spoiler

240p test suite @ 480i, no verifiable difference:

Spoiler

Lastly, GBS-8200 CFW output set to 640x480 mode (supported resolution for SM930b). The same process chain as immediately above, but with the 480p line doubling and upsample2x enabled at the OSSC. No verifiable difference:

Spoiler