shmups.system11.org

CPS2 mainboard has digital video (384x224, 4bpc) and audio (24kHz i2s) readily available, making it relatively easy to losslessly hook the system up to a modern display. I've been working on a small add-on board that handles necessary format conversions, currently implementing integer scaling to HDTV formats (480p/720p/1080p/1200p) and audio upsampling to 48kHz.

There are some extra features that are planned which should be doable with little or no additional hardware:

-CEA timings compliancy (excl. refresh rate)
-non-integer scaling
-scanline overlay
-OSD plus control via CPS2 side buttons

The PCB still needs 1-2 revisions before it can be considered release quality. Ideally it could be fitted inside CPS2 case with just one extra hole for HDMI connector. Board design files, gerbers, firmware etc. will all be freely available once the project is more mature. Below is a couple photos of the current prototype (click for bigger versions).



Also, big thanks for undamned for providing CPS2 hardware for the project.

Hooray ! Digital audio on CPS2 !
Well digital video will also be very nice.

Keep up the good work !

awesome!

Amazing as usual

Incredible work. That's a beautiful board design. I'd love to add this to my Darksoft rig.

I was just thinking the same thing. My gosh, all CPS2 games--arcade-perfect--on virtually any display. Sounds awesome.

Very impressive!

As long as sub-frame input lag, <3 this. Can't wait for the schematics so I can possibly stick this on a breadboard myself.

I need to follow this closely. Great work! Let me know if you want/need any help with manufacturing, etc. Between this, the CPS2 MultiKit, and the new case I designed for them I see a very slick DIY (easily built) kit possible.

Jasen

This looks great. Are you scaling with a buffer to 1080p, or are you doing a line multiplier with tight timings?

This is awesome news.
The resolution could be upscaled by 500%
That will get
1920X1120
It means you will lose (1120-1080) 40 lines on the top and bottom of the screen.
But regarding the source it would be just horizontal 8 lines less.
Not sure how bad the cps-II video will look with 4 lines cropped from the top and 4 lines cropped from the bottom.

300% will get you.
1152X672

not all displays support 4:3 AR for 16:9 source material and many users prefer to play CPS2 slightly wider than 4:3.

Thanks for the proposal. I was planning to just release the project as a DIY design once it's nearer completition, but if there's enough interest then it might make sense to look into manufacuring pre-assembled boards as well.

Currently it's a simple line multiplier, so basically no latency but not perfect display compatibility either. The FPGA has enough block RAM to store at least 40 input scanlines, so buffering can be used to resolve line count discrepancies up to 1080p. Generation of suitable pixel clock will be more challenging: e.g. for frame-locked 1080p output, 2200*1125=2475000 pixel clock cycles should ideally be generated each frame while CPS2 outputs 512*262=134144 cycles. Exact (2475000/134144)=(309375/16768) ratio is probably unattainable even with a cascade of fractional PLLs, but I have 2 ideas I've been planning to try out:

1. Generation of near-ideal pixel clock (e.g. 147.6MHz for 1080p), and then dynamically adjusting one blanking line length to keep output frame-locked. Not sure how displays will react to this. Probably at least some will accept that fine if adjustment is no more than a couple pixels.

2. Slightly relaxed CEA timings to allow suitable PLL ratio. In thet 1080p example, total output width of 2227 would allow ratio of (2505375/134144)=(19125/1024)=(153/32)*(125/32) which should be implementable with 2 cascaded PLLs.

Suitable integer-multiplied resolutions for near-correct aspect ratio are 1152x896 and 1536x1120, the former fitting nicely into 1280x960 frame and the latter almost nicely into 1920x1080 frame.

Any time. I have a number of good quality manufacturing contacts both inside the US and out that I have used for my small contributions to the hobby. Might be a good resource for those that are a bit less adept at soldering, manufacturing, and sourcing parts or simply don't want to deal with it. In any case, Ill be getting at least one made up to install and test out.

Thank you marqs for just another amazing project!

Most cps games at 1120 fit amazingly well on a 1080 panel... IF you can switch/pan the image up or down a few lines.
Because sometimes health bars/meters are placed either at the top or the bottom.

Very cool. Looking foreward to this. CPS II is my favorite arcade hardware.

Brief discussion about the board and installation:

https://www.youtube.com/watch?v=xfkiiweuuns

-ud

This is amazing.

Rough 1080p Demo (on a BenQ RL2460):

https://www.youtube.com/watch?v=jZYCWEWsxYw

-ud

Performance compared to a CRT setup:

https://www.youtube.com/watch?v=4h3o1Hf1HDg

-ud

Wow, that's really impressive. I'd buy one.

A small progress report:

I'm planning to publish files for the version shown on the first post in a couple weeks since hw/code has been working stable for a while now. I just need to clean things up a bit and add an OSD to enable dynamically changing settings such as 640x480/1080p selection, scanlines etc.

However, I'll be making an updated PCB after that with the following changes:

* Add Si5351C clock generator. With that it's possible to generate exact fractional ratios for CEA 720p/1080p modes, meaning full compatibility with HDTVs as long as they support 59.63Hz refresh rate.
* Replace IT6613E HDMI transmitter with ADV7513. The latter is smaller in size and has better availability.

The second revision is the one development will eventually switch to, so most people probably will want to wait for that.

Exciting stuff. How does the clock generator work? Can it be implemented on the OSSC to help with compatibility?
Can a more generic version be made with 8bpp? Like for a 3DO?
You might be starting a new level of modding. It started with everyone looking for analog RGB in consoles. Now they will be looking for the digital lines before the encoder.

Si5351C has quite flexible 2-stage clock synthesis, allowing accurately setting the ratio by which input clock (16MHz in CPS2 case) is multiplied. It could be used with OSSC as well (with some extra line buffers), but then the parameters would need to be calculated dynamically to allow various sources and sampling rates.
By utilizing some unused FPGA inputs the board could be easily made to process digital 24bit RGB/YCbCr sources in general.
Many consoles with digital RGB extractable already have such mods, e.g. NES, N64, DC, GC, Wii.

Code and pcb files for first revision are now publicly available. OSD is not yet implemented so currently functions are directly mapped to CPS2 vol+/- buttons.

Awesome work!

Have you already planned when it will be available the next hardware revision (ADV7513, Si5351C, etc.)?

You are a champ, sir! Continued thanks for all your work on this project!
-ud

Very impressed.

Updating PCB design with those parts shouldn't be a big task, but I'm awaiting some feedback from the current revision before starting that.