I have the board hooked up to my SNES
https://imgur.com/a/sLS4o . I can get a full SNES frame showing, but it rolls through the screen diagonally which means the timing isn't synced up. There's also a TON of noise, but that is slowly going away as sampling issues get fixed. I will say, a line buffer design with HDMI is a lot trickier than a frame buffer design...props to those who have made line doublers.
-------------sync issues----------------------
I don't think it would be hard to solve the rolling frames if I had proper sync signals from the SNES. I think something may be wrong with my lmh1980 as the hsync output pin gives a garbage output and vsync gives a delayed hsync (if I try to sample line data on the lmh1980 vsync output, it works but the beginning of the line is missing). I'm taking csync from the via next to the RGB vias, I put a series 75ohm resistor on the csync line which feeds into the LMH1980 with a 75ohm resistor on input to ground. If anyone can give some insight that might help with my lmh1980 issues that would be great.
------------------------------------------------
-------------Clock issues----------------------
Since I have video working out of the line buffer (just needs to be synced) I figured I would work on sending a clock to the SNES from the FPGA. Direct 3.3v connection from FPGA didn't work (SNES wouldn't boot up), putting it through a 3.3-> 5v shifter didn't work either. Then I decided to measure the crystal on my other snes, it read 1.8v, should I try using that? I was able to take cart pin 1 from my unmodded snes and use it to clock the SNES without a crystal, the SNES then booted up great. This somewhat confirms that the SNES can work from a single-ended non crystal clock.
Do you think it's a voltage level issue or a termination issue with the clock coming from the FPGA?
Another thing I noticed, the SNES crystal/clock needs to be running when the SNES is powered on. Meaning the FPGA which provides the clock needs to be configured and ready before the SNES, if the clock starts after the SNES power is switched on then the SNES doesn't boot up (in my quick tests). If the clock is lost the SNES crashes. This is much different than the GBA which can run clockless after boot-up and the GBA doesn't mind dropped clocks at all. I think basic power sequencing will be needed in the final design to ensure the FPGA is powered up and configured before the SNES.
----------------------------------------------------
-------------------Future plans-------------------
Assuming I can solve the above issues...My general plan of attack is to clock the SNES with a ~21Mhz clock from the FPGA, then use that clock inside the FPGA to generate the frame/line timing info that the SNES uses, so I have a timing reference for writing/reading from the line buffer.
----------------------------------------------------
------------------Current pics--------------------
Anyway here's some not-very-exciting pics of current progress.
http://imgur.com/a/0jc6N You can see the noise and misalignment issues (due to rollin frame) I was talking about. The 2nd black and white picture is the composite output of the SNES clocked from FPGA, usually it doesn't boot...but if I connect the unused crystal pin with a series capacitor to ground then it boots and I get this lovely garbage. The HDMI output has normal colors in this instance, just composite gets destroyed. Still trying to figure it all out.
